With gradually scaling down of the critical dimensions of semiconductor devices to provide more functions within an effective area of semiconductor devices, 3D packaging techniques are developed. 3D packaging allows more semiconductor functions to be packed in a given volume. In 3D packaging, a PCB substrate and another substrate are welded together by soldered balls so that bonding wires are not needed, which allows significant size and weight reduction smaller and increase in operating speeds through improved communication between chips. In a prior art technique, semiconductor devices meeting process requirements are first produced, and they are then packaged together using a plastic packaging process or a ceramic packaging process.
FIG. 1 to FIG. 4 are schematic cross-sectional views of intermediate structures illustrating a method for manufacturing a semiconductor device, as known in the prior art. As shown in FIG. 1, a posterior interconnect layer 11 is formed on a surface of a first substrate 10. A weld pad 12 is formed in the posterior interconnect layer 11, then, a semiconductor component that is formed in the first substrate 10 are electrically connected with the weld pad 12.
Afterwards, the posterior interconnect layer 11 of the first substrate 10 is bonded with a second substrate 13 to form an original integral semiconductor device. A thinning process is performed on a surface of the first substrate 10 that is facing away from the second substrate 13 to obtain a desired thickness of the first substrate 10.
Thereafter, a plasma etching process is performed on the thinned surface of the first substrate 10 to form a via, as shown in FIG. 2.
Referring to FIG. 3, a dielectric layer 16 is formed on the surface of the first substrate and on sidewalls of the via. Then, the via is filled with an interconnect layer 14, which covers the dielectric layer 16.
Thereafter, referring to FIG. 4, a conductive bump 15 is formed and the conductive bump 15 is electrically connected with the interconnect layer 14.
Generally, after the conductive bump 15 is formed, a packaging process is performed. However, in the prior art, a semiconductor device thus formed has low reliability that affects the reliability of 3D packages of the semiconductor devices.